1. Field of the Invention
The invention is relates to a floating gate, and more particularly to a floating gate with multiple tips and a fabrication method thereof.
2. Description of the Related Art
Memory devices for non-volatile storage of information are currently in widespread use, in a myriad of applications. A few examples of non-volatile semiconductor memory include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) and flash EEPROM.
An advantage of EPROM is electrical programmability, but for erasing, EPROM requires exposure to ultraviolet (UV) light.
In many circuit designs it is desirable to have a non-volatile memory device that can be erased and reprogrammed in-circuit, without the need to remove the device.
EEPROM devices have the advantage of electrical programming and erasing, achieved by charging and discharging actions controlled by the control gate. The actions also affect the conductivity of the channel between source and drain.
One of the advantages of flash memory is its capacity for block-by-block memory erasure. Furthermore, memory erasure is fast, normally taking just 1 to 2 seconds for the complete removal of a whole block of memory. Another advantage of the flash memory is low power consumption. The voltages of a control gate, a source, and a drain are adjusted to program or erase in a split gate flash memory.
FIGS. 1a to 1c are cross-sections of the conventional method of fabricating a floating gate of a split gate flash memory.
In FIG. 1a, a silicon substrate 101 is provided. A gate oxide layer 102, a doped polysilicon layer 103, and a nitride layer 104 having an opening 105 are sequentially formed on the silicon substrate 101.
In FIG. 1b, the doped polysilicon layer 105 exposed by the opening 105 is oxidized to form an oxide layer 106 with a Bird's Beak shape edge.
In FIG. 1c, the nitride layer 104 is removed. The doped polysilicon layer 103 is anisotropically etched to form a floating gate 103a using the oxide layer 106 as an etching mask.
A split gate flash memory is completed after a control gate is formed on the floating gate and the silicon substrate 101 is implanted to form source/drain devices.
In the program step, high voltage is applied between the source and drain. Another high voltage is applied to the control gate and goes to the floating gate because of the electric capacity coupling, and a high electric field is produced on the film gate oxide layer. The electricity is injected into the floating gate through the film gate oxide layer from the drain.
In the erase step, a high voltage is applied between the drain and the control gate. A high electric field is produced on the film gate oxide layer because of the electric capacity coupling. The electricity injects into the drain through the film gate oxide layer from the floating gate, such that the gate oxide layer is damaged by the high voltage.
When the edge of the floating gate is a tip, the electric field is easily concentrated in the tip, and the point is easily discharged. If the point discharge is increased, the erase effect is strong.
In addition, die size is larger due to the addition of programming circuitry and there are more processing and testing steps involved in the manufacture of these types of memory devices.